As densities of memories increase it is important that power consumption be minimized and that memory timing schemes be maximized to ensure good speed and efficiency of memory operation.
FIG. 1a illustrates a block diagram of a conventional dynamic random access memory (DRAM) multiplexing input buffer circuit which may lie on an intergrated circuit chip. As shown, input buffer 2 for receiving a row address selection (RAS) signal is connected to a node, such as bond pad 3, for receiving address signal ADD. Likewise, input buffer 4 for receiving a column address selection (CAS) signal is connected to the same node, or rather bond pad 3. The output from RAS input buffer 2 is transmitted to and decoded by a row decoder (not shown). In a similar manner, the output from CAS input buffer 4 is transmitted to and decoded by a column decoder (not shown). Alternatively, the outputs of buffers 2 and 4 may be sent to other circuitry internal to the memory, i.e. a driver preceding a row decoder and etc. The address placed on bond pad 3 is multiplexed to either RAS input buffer 2 or CAS input buffer 4 in connection with clock signals 0RAS1 and 0CAS1 to their respective input buffers. For instance, when 0RAS1 is at a logic high level, RAS input buffer 2 will accept the address information from bond pad 3. Similarly, CAS input buffer 4 accepts address information from bond pad 3 when 0CAS1 is at a high level. Information to the respective input buffers is latched in connection with the receipt of second clock signals 0RAS2 and 0CAS2. For example, RAS input buffer 2 latches the address presented at bond pad 3 when it receives a logic high 0RAS2 signal. Likewise, CAS input buffer 4 latches the address presented at bond pad 3 upon receipt of a logic high 0CAS2 signal. Thus, an input buffer, after latching the information from bond pad 3 will n longer respond to further address changes. Additionally, upon latching its information, the buffer will turn off to avoid further d.c. power consumption. Clock signals 0RASl and 0RAS2 are generated by a clock 6. Additionally, clock signals 0CAS1 and 0CAS2 are generated by a clock 8.
In order to explain the problems associated with prior art input buffer circuits, reference shall now be made to FIG. 1b which illustrates a timing diagram for operation of the circuit shown in FIG. 1a. Clock signals 0RAS1, 0RAS2, 0CAS1, 0CAS2 and address signal ADD are shown changing between logic high levels, represented by V.sub.H, to logic low levels, represented by V.sub.L, with respect to time. An arrow from one graph to another indicates that the signal associated with the graph from which the arrow terminates, is derived from the signal associated with the graph from which the arrow originates. For example, 0RAS2 is derived from 0RAS1, and 0CAS2 is derived from 0CAS1. Thus, clock 6 must generate a timing delay between signals 0RAS1 and 0RAS2. Similarly, clock 8 must generate a timing delay between signals 0CAS1 and 0CAS2. These timing delays between clock signals for each input buffer are derived without feedback from the input buffers. Prior art schemes which implement a timing delay between clock signals to an input buffer have consisted of circuitry which inherently loads the clock. This heavy loading results in timing delays between the 0RAS1 and 0RAS2 signals as well as between the 0CAS1 and 0CAS2 signals which are not accurate. Such inaccuracies can result in unnecessary delay which slows the overall operation of the memory and more specifically, input buffer operation.